Explanation why GraniteBay is superior to Nforce

[BrwmogazoS]

Ta 8erma mou sygxarhthria sto Bill gia to Copy Paste :grin:...

 

From OCUK:

 

http://www.lostcircuits.com/motherb...s_p4g8x/2.shtml

 

I have said this again and again- the Norce is NOT a proper dual channel solution, with bandwidth thats no better than single channel DDR of a PIV (fsb for fsb), and this explains why:

 

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Dual Channel DDR support a la Intel is fundamentally different from nVidia's TwinBank Architecture. In the latter, two independent memory buses are operating, with Intel's solution, two DIMMs are recognized as one single 128 bit wide entity, that is the "άberDIMM" meaning that each page that is opened is also 128 bit wide and every transfer will encompass the full bandwidth. In case two different density DIMMs are being used, that is, a single-sided and a double-sided DIMM, the controller can't but ignore the smaller DIMM, otherwise it would have to toggle between 64bit and 128bit transfers and at some point try to write 128 bits into a 64 bit memory space or vice versa. That would leave it confused.

 

The E7205 memory controller has no need for an arbiter and does not show separate memory controllers in the device manager either. According to the Intel white papers, a memory configuration utilizing both channels (A and will be seen by the memory controller as a single bank spanning across both DIMM slots. That is, each row (the term used by Intel) is 128 bit (data) wide. Of course, this causes the problem of how a 128 bit wide burst of data is going to be funneled through a 64 bit interface. Keep in mind, though that the external CPU bus is running at twice the data rate (QDR instead of DDR) and, therefore, the 128 bit data chunk can be split into two 64 bit transactions on back-to-back transfers. Also keep in mind that the utilization of the 128 bit interface will require the presence of two identical DIMMs at least with respect to their configuration. That does not mean that both DIMMs have to be from the same vendor, it is certainly possible to combine DIMMs of similar quality, e.g. a Corsair with an OCZ DIMM, they will be running in DDR266 mode anyway. However, different format DIMMs cannot be run in the complementary channels, that is, if slot A1 is populated with one double-sided 512 MB DIMM and slot B1 with a 256 MB single-sided DIMM, the latter will not be seen by the chipset.

 

 

[Narayan]

Πολύ κακό για το τίποτα. Αφού ο δίαυλος είναι 64bit ποιό το νόημα να χρησιμοποιείται 128bit για τα memory pages; Για την μετέπειτα ανάγνωση των δεδομένων από τη CPU θα πρέπει να ξανακοπεί η page σε 2x64bit packets, με αποτέλεσμα, όπως αναφέρεται παραπάνω, να συμπεριφέρεται η QDR 64bit διαμεταγωγή ως DDR 128bit! Δηλαδή δεν υπάρχει ουσιαστικό όφελος, κάτι που επιβεβαιώνεται και από τις μετρήσεις των σχετικών mobo.

ΙΜΗΟ, μια φαινομενικά απλή λύση για επεξεργαστές με HyperThreading είναι η ύπαρξη δύο pipeline με τη μνήμη, με κάθε DIMM να διαχειρίζεται από το αντίστοιχο thread του επεξεργαστή και να γίνεται παράλληλη επεξεργασία. Γνωρίζει κανείς αν αυτό είναι εφικτό;